Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.

Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 12, 1 (2004).
Päätekijä: Taskin, B.
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
ISCAS89 benchmark circuits.
MBM.
Big M method.
Clock period minimization.
Flip-flop based circuits.
Industrial LP solver CPLEX.
Large scale synchronous circuits.
Level sensitive circuits.
Level sensitive digital synchronous circuits.
Level sensitive latches.
Linear programming.
Linearization.
Multiphase clocking schemes.
Nonzero clock skew scheduling.
Optimization.
Singlephase clocking schemes.
Time borrowing.
Timing analysis.
Zero clock skew.