LECTOR a technique for leakage reduction in CMOS circuits.
In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasi...
Izdano u: | IEEE Transactions on VLSI systems 12, 2 (2004). |
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Glavni autor: | |
Format: | Članak |
Jezik: | English |
Teme: |