Circuit and microarchitectural techniques for reducing cache leakage power.

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. As feature sizes shrink, the dominant component of this power consumption will be leakage. However, during a fixed period of time, the activity in a data cache is only centered on a small subset of the lin...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:	IEEE Transactions on VLSI systems 12, 2 (2004).
Prif Awdur:	Nam Sung Kim
Fformat:	Erthygl
Iaith:	Saesneg
Pynciau:	CMOS process. SRAM. Cache leakage power reduction. Circuit techniques. Control strategies. Drowsy data caches. Drowsy instruction caches. Low power. Low-leakage drowsy mode. Microarchitectural techniques. Microprocessor power consumption. On-chip caches. Short-channel effects. Subthreshold leakage power. Voltage scaling.