Statistical analysis of subthreshold leakage current for VLSI circuits.

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributi...

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Bibliografski detalji

Izdano u:	IEEE Transactions on VLSI systems 12, 2 (2004).
Glavni autor:	Rao, R.
Format:	Članak
Jezik:	English
Teme:	CMOS gates. Monte Carlo simulation. VLSI circuits. Gate length process variability. Probability density function. Stacked devices. Statistical analysis. Subthreshold leakage current.