Scaling trends of on-chip power distribution noise.

Scaling trends of on-chip power distribution noise.

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 4 (2004).
Main Author: Mezhiba, A.V
Format: Article
Language:English
Subjects:
Flip-chip packaged integrated circuits.
Flip-chip pad density.
High-performance integrated circuits.
Inductive voltage drops.
Multilayer interconnect.
On-chip power distribution noise.
Power supply noise.
Resistance voltage drops.
Scaling trends.
Signal integrity.
Technology scaling.