Modeling subthreshold SOI logic for static timing analysis.

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pse...

Полное описание

Библиографические подробности
Опубликовано в::	IEEE Transactions on VLSI systems 12, 6 (2004).
Главный автор:	Valentian, A.
Формат:	Статья
Язык:	английский
Предметы:	CMOS digital integrated circuits. MOSFET. SOI logic. SPICE simulations. Analytical expressions. Complementary metal-oxide-semiconductor. Integrated circuit modelling. Logic delay. Logic switching. Low-power electronics. Metal-oxide-semiconductor field effect transistor. Pseudosaturation regions. Pseudotriode regions. Short channel effect. Silicon on insulator logic. Simulation program with integrated circuit. Static timing analysis. Subthreshold drain current.