An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
The input referred offset voltage occurring in the full latch VDD biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by ±2.5% variation in VT and ±5% variation in β, from typical values. Effect of various design p...
| Xuất bản năm: | IEEE Transactions on VLSI systems 12, 6 (2004). |
|---|---|
| Tác giả chính: | |
| Định dạng: | Bài viết |
| Ngôn ngữ: | English |
| Những chủ đề: |