An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.

An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.

The input referred offset voltage occurring in the full latch VDD biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by ±2.5% variation in VT and ±5% variation in β, from typical values. Effect of various design p...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 6 (2004).
Main Author: Singh, R.
Format: Article
Language:English
Subjects:
SRAMs.
Design parameters.
Metal oxide semiconductor transistor.
nMOS transistors.
Offset compensation technique.
Offset voltage.
pMOS transistors.
Power consumption.
Sense amplifier enable signal.
Static random access memory.
Full latch VDD biased sense amplifier.