Implicit deductive fault simulation for complex delay fault models.

Implicit deductive fault simulation for complex delay fault models.

This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit tr...

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Bibliografiska uppgifter
I publikationen:IEEE Transactions on VLSI systems 12, 6 (2004).
Huvudupphovsman: Deodhar, J.V
Materialtyp: Artikel
Språk:English
Ämnen:
Data structures.
Fault coverage.
Implicit deductive fault simulation.
Path delay fault models.
Segment delay fault model.
Subset.
Topological circuit traversal.