Test data compression technique for embedded cores using virtual scan chains.

This paper presents a design-for-test (DFT) technique to implement a "virtual scan chain" in a core that looks (to the system integrator) like it is shorter than the real scan chain inside the core. A core with a "virtual scan chain" is fully compatible with a core with a regular...

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Τόπος έκδοσης:	IEEE Transactions on VLSI systems 12, 7 (2004).
Κύριος συγγραφέας:	Jas, A.
Μορφή:	Άρθρο
Γλώσσα:	English
Θέματα:	DFT technique. Design for testability. Embedded core testing. External test interface. Scan shift cycle. System integrator. Test data compression technique. Tester program. Virtual scan chain. Virtual scan vector.