Test data compression technique for embedded cores using virtual scan chains.

Test data compression technique for embedded cores using virtual scan chains.

This paper presents a design-for-test (DFT) technique to implement a "virtual scan chain" in a core that looks (to the system integrator) like it is shorter than the real scan chain inside the core. A core with a "virtual scan chain" is fully compatible with a core with a regular...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 12, 7 (2004).
Päätekijä: Jas, A.
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
DFT technique.
Design for testability.
Embedded core testing.
External test interface.
Scan shift cycle.
System integrator.
Test data compression technique.
Tester program.
Virtual scan chain.
Virtual scan vector.