Jas, A. Test data compression technique for embedded cores using virtual scan chains. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationJas, A. "Test Data Compression Technique for Embedded Cores Using Virtual Scan Chains." IEEE Transactions on VLSI Systems .
MLA citiranjeJas, A. "Test Data Compression Technique for Embedded Cores Using Virtual Scan Chains." IEEE Transactions on VLSI Systems, .
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