High performance level conversion for dual VDD design.

High performance level conversion for dual VDD design.

Multi-VDD design is an effective way to reduce power consumption, but the need for level conversion imposes delay and energy penalties that limit the potential gains. In this paper, we describe new level converting circuits that provide 10%-61% lower energy consumption at equivalent or better speeds...

全面介绍

书目详细资料
发表在:IEEE Transactions on VLSI systems 12, 9 (2004).
主要作者: Kulkarni, S.H
格式: 文件
语言:English
主题:
Benchmark circuits.
Delay circuits.
Dualvoltage design.
Energy consumption.
Gate circuit.
High performance level conversion.
Level converters.
Level converting circuits.
Logic gates.
Multivoltage design.
Power consumption.
Timing slack.