On circuit techniques to improve noise immunity of CMOS dynamic logic.

On circuit techniques to improve noise immunity of CMOS dynamic logic.

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, t...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Transactions on VLSI systems 12, 9 (2004).
Prif Awdur: Li Ding
Fformat: Erthygl
Iaith:English
Pynciau:
1.0 V.
1.6 V.
VLSI chips.
Aggressive technology scaling.
Circuit techniques.
Deep submicron process technology.
Differential resistance effect.
Dynamic CMOS logic circuits.
Dynamic CMOS logic gates.
Dynamic circuits.
Dynamic logic gates.
Noise immunity.
Noise tolerance.
Static CMOS logic gates.