A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-VTHP pMOS transistors, while the bitline drivers are realized by a pair of low-VTHN nMOS transistors. The wordline...

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Publicado no:	IEEE Transactions on VLSI systems 12, 9 (2004).
Autor principal:	Chua-Chin Wang
Formato:	Artigo
Idioma:	English
Assuntos:	4 kB. 500 MHz. CMOS SRAM cell. Bitline boosting circuit. Bitline drivers. Cascaded noise-immune address transition detector. Chip select glitches. Cross coupled high-voltage pMOS transistors. Data retention. Dual threshold voltage transistors. External refreshing mechanism. Latches. Low-voltage nMOS transistors. Memory cells. Self-refreshing paths. Wordline voltage compensation circuit.