Critical evaluation of SOI design guidelines.

Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to...

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Bibliographic Details

Published in:	IEEE Transactions on VLSI systems 12, 9 (2004).
Main Author:	Kanj, R.
Format:	Article
Language:	English
Subjects:	SOI design guidelines. SOI domino circuits. SOI technology. Si. Adder designs. Bipolar leakage induced upset. Bulk-silicon. Charge sharing problem. Domino logic. Domino silicon-on-insulator CMOS circuits. Logic gates. Noise tolerance. Parasitic bipolar induced upset. Static silicon-on-insulator CMOS circuits.