Effects of speculation on performance and issue queue design.
Current trends in microprocessor designs indicate increasing pipeline depth in order to keep up with higher clock frequencies and increased architectural complexity. Speculatively issued instructions are particularly sensitive to increases in pipeline depth. In this brief, we use load hit speculatio...
| Published in: | IEEE Transactions on VLSI systems 12, 10 (2004). |
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| Main Author: | |
| Format: | Article |
| Language: | English |
| Subjects: |