Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circui...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 12, 10 (2004).
Main Author: Heydari, P.
Format: Article
Language:English
Subjects:
CML latches.
Analytical models.
High speed regenerative latch circuits.
High-speed low-voltage application.
Latch architectures.
Ultrahigh speed data rates.
Ultrahigh speed low voltage CMOS CML buffers.