Power estimation techniques for FPGAs.

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical predic...

पूर्ण विवरण

ग्रंथसूची विवरण
में प्रकाशित:	IEEE Transactions on VLSI systems 12, 10 (2004).
मुख्य लेखक:	Anderson, J.H
स्वरूप:	लेख
भाषा:	अंग्रेज़ी
विषय:	FPGA design. FPGA interconnect architecture. Capacitance prediction. Digital CMOS circuit. Dynamic power consumption. Electronic engineering computing. Field programmable gate array. Interconnect capacitance. Logic delay activity. Noise limitations. Power aware layout synthesis. Power estimation. Prediction models. Switching activity. Zero delay activity.