Power estimation techniques for FPGAs.

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical predic...

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Publié dans:	IEEE Transactions on VLSI systems 12, 10 (2004).
Auteur principal:	Anderson, J.H
Format:	Article
Langue:	English
Sujets:	FPGA design. FPGA interconnect architecture. Capacitance prediction. Digital CMOS circuit. Dynamic power consumption. Electronic engineering computing. Field programmable gate array. Interconnect capacitance. Logic delay activity. Noise limitations. Power aware layout synthesis. Power estimation. Prediction models. Switching activity. Zero delay activity.