Power estimation techniques for FPGAs.
The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical predic...
| Foilsithe in: | IEEE Transactions on VLSI systems 12, 10 (2004). |
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| Príomhchruthaitheoir: | |
| Formáid: | Alt |
| Teanga: | English |
| Ábhair: |