Interconnect accelerating techniques for sub-100-nm gigascale systems.
This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current an...
| Foilsithe in: | IEEE Transactions on VLSI systems 12, 11 (2004). |
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| Príomhchruthaitheoir: | |
| Formáid: | Alt |
| Teanga: | English |
| Ábhair: |