Interconnect accelerating techniques for sub-100-nm gigascale systems.

This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current an...

पूर्ण विवरण

ग्रंथसूची विवरण
में प्रकाशित:	IEEE Transactions on VLSI systems 12, 11 (2004).
मुख्य लेखक:	Hong-Yi Huang
स्वरूप:	लेख
भाषा:	English
विषय:	100 nm. RC delay circuits. Bidirectional interface. Capacitor coupling accelerator circuits. Capacitor coupling trigger circuits. Complex dynamic logic circuits. Field programmable gate array interconnections. Gate threshold voltage. Gigascale systems. Interconnect accelerating techniques. Multiports bus. Output driving paths. Output driving transistors. Short circuit current. Signal transition time.