Bus-switch coding for reducing power dissipation in off-chip buses.

We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving off-chip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reordering of bus line positions, in order to minimize the togg...

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Pubblicato in:	IEEE Transactions on VLSI systems 12, 12 (2004).
Autore principale:	Olivieri, M.
Natura:	Articolo
Lingua:	inglese
Soggetti:	Bus line positions. Bus power dissipation reduction. Bus switch coding. Circuit simulation. Hardware description languages. Line capacitance. Minimization. Off-chip buses. Physical bus wires. Post layout evaluation.