Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.
High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in...
| 發表在: | IEEE Transactions on VLSI systems 13, 1 (2005). |
|---|---|
| 主要作者: | |
| 格式: | Article |
| 語言: | English |
| 主題: |