Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.

Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in...

Ausführliche Beschreibung

Bibliographische Detailangaben
Veröffentlicht in:IEEE Transactions on VLSI systems 13, 1 (2005).
1. Verfasser: Lok-Kee Ting
Format: Artikel
Sprache:English
Schlagworte:
120 MHz.
DLMS algorithm.
LMS recursive system.
Adaptive least mean square filter.
Delayed LMS algorithm.
Direct form.
Electronic support measures digital receivers.
Fine-grained pipelining.
High speed field programmable gate array implementation.
High-speed Virtix FPGA implementation.
Output latency.
Pipelined adaptive LMS predictor.
Processor.
Sampling rate.
Transposed form.