Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.
High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in...
| 发表在: | IEEE Transactions on VLSI systems 13, 1 (2005). |
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| 格式: | 文件 |
| 语言: | English |
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