Current demand balancing a technique for minimization of current surge in high performance clock-gated microprocessors.

We propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorp...

Szczegółowa specyfikacja

Opis bibliograficzny

Wydane w:	IEEE Transactions on VLSI systems 13, 1 (2005).
1. autor:	Yiran Chen
Format:	Artykuł
Język:	English
Hasła przedmiotowe:	0.18 micron. 90 micron. Current surge minimization. Decoupling capacitance. Dynamic functional unit selection. Floorplan. High performance clock gated microprocessors. Instructions per cycle. Integrated architectural planning approach. Issue pattern management. Peak noise. Priority assignment optimization. Submodule design.