Current demand balancing a technique for minimization of current surge in high performance clock-gated microprocessors.
We propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorp...
| প্রকাশিত: | IEEE Transactions on VLSI systems 13, 1 (2005). |
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| প্রধান লেখক: | |
| বিন্যাস: | প্রবন্ধ |
| ভাষা: | English |
| বিষয়গুলি: |