APA (7th ed.) Citation

Agarwal, A. A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Transactions on VLSI systems.

Chicago Style (17th ed.) Citation

Agarwal, A. "A Process-tolerant Cache Architecture for Improved Yield in Nanoscale Technologies." IEEE Transactions on VLSI Systems .

MLA (9th ed.) Citation

Agarwal, A. "A Process-tolerant Cache Architecture for Improved Yield in Nanoscale Technologies." IEEE Transactions on VLSI Systems, .

Warning: These citations may not always be 100% accurate.