A transaction-based unified architecture for simulation and emulation.
The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for...
| 出版年: | IEEE Transactions on VLSI systems 13, 2 (2005). |
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| 第一著者: | |
| フォーマット: | 論文 |
| 言語: | 英語 |
| 主題: |