Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.

This paper demonstrates how IEEE 754 floating-point standard compliant rounding can be merged with carry-propagate addition in floating-point unit (FPU) designs by using a novel adaptation of the prefix adder. The paper considers add/subtract, multiply, and SRT divide operations and demonstrates tha...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 2 (2005).
第一著者:	Burgess, N.
フォーマット:	論文
言語:	English
主題:	IEEE 754 floating-point standard. IEEE floating point operations. Addition-subtraction operation. Carry propagate addition. Contemporary pipelined floating point unit design. Critical path analysis. Divide operations. Flagged prefix adder. Generic rounding architecture. Multiply operation. Prenormalization rounding. Rounding modes.