A micropower low-voltage multiplier with reduced spurious switching.

A micropower low-voltage multiplier with reduced spurious switching.

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit de...

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Détails bibliographiques
Publié dans:IEEE Transactions on VLSI systems 13, 2 (2005).
Auteur principal: Kwen-Siong Chong
Format: Article
Langue:English
Sujets:
0.35 micron.
1.1 V.
5 MHz.
Adder block.
Chronological sequence.
Energy-delay-product.
External latches.
Hardware penalty.
Hearing aids.
Latch adder.
Low-voltage power-critical low speed applications.
Micropower low-voltage multiplier.
Micropower multiplier design.
Micropower operation.
Prototype IC.
Reduced spurious switching.
Three metal dual poly CMOS process.