Design of a 3-D fully depleted SOI computational RAM.

Design of a 3-D fully depleted SOI computational RAM.

We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast gl...

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Publicat a:IEEE Transactions on VLSI systems 13, 3 (2005).
Autor principal: Koob, J.C
Format: Article
Idioma:English
Matèries:
128 kbit.
3D fully depleted SOI computational RAM.
3D processor-in-memory integrated circuit design.
400 MHz.
Si.
Fast global bus evaluation.
Integrated circuit testing.
Interconnect length reduction.
Memory architecture.
Nearest neighbor physical 3D communication network.
Parallel processing.
Processor-memory redundancy.
Silicon on insulator dies.
Stacked dies.