On the impact of on-chip inductance on signal nets under the influence of power grid noise.

On the impact of on-chip inductance on signal nets under the influence of power grid noise.

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of...

Description complète

Détails bibliographiques
Publié dans:IEEE Transactions on VLSI systems 13, 3 (2005).
Auteur principal: Chen, T.
Format: Article
Langue:English
Sujets:
0.13 micron.
0.18 micron.
Al.
Al-based CMOS process.
Al-based interconnect technology.
Cu.
Cu-based CMOS process.
Cu-based interconnect technology.
Heuristic method.
On-chip inductance.
Power grid noise.
Power supply network.
Signal delay modeling.
Signal delay simulation.
Signal nets.
Ultradeep submicron technology.