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Self-reset logic for fast arithmetic applications.

A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also proposed. These cells maintain small delay variations...

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Bibliografske podrobnosti
izdano v:IEEE Transactions on VLSI systems 13, 4 (2005).
Glavni avtor: Litvin, M.E
Format: Article
Jezik:angleščina
Teme:
Asynchronous circuits.
Clocking overhead reduction.
Control circuits.
Data-path circuits.
Delay variations.
Dual-rail SRL.
Dual-rail logic.
Dynamic logic.
Fast arithmetic applications.
Logic depth.
Process variation.
Pulsed logic.
Self-reset logic.
Self-timed circuits.
Single-ended structure.
Supply voltage variation.
Temperature variations.
Varying fanout.
Wave pipelining.