VLSI architectural design tradeoffs for sliding-window log-MAP decoders.

VLSI architectural design tradeoffs for sliding-window log-MAP decoders.

Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying soft-input soft-output decoding algorithms usu...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Transactions on VLSI systems 13, 4 (2005).
Prif Awdur: Chien-Ming Wu
Fformat: Erthygl
Iaith:English
Pynciau:
3G mobile radio.
MAP algorithm.
VLSI architecture.
Area/computation complexity.
Decoding rate.
Error-correcting capability.
Iterative decoder.
Latency performance.
Memory power consumption.
Sliding-window log-MAP decoders.
Soft-input soft-output decoding.
Turbo codes.