Schedule-aware performance estimation of communication architecture for efficient design space exploration.

In this paper, we are concerned about performance estimation of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable due to bus contention, a simulation-based appr...

Deskribapen osoa

Xehetasun bibliografikoak
Argitaratua izan da:IEEE Transactions on VLSI systems 13, 5 (2005).
Egile nagusia: Sungchan Kim
Formatua: Artikulua
Hizkuntza:ingelesa
Gaiak: