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Layout conscious approach and bus architecture synthesis for hardware

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such a...

詳細記述

書誌詳細
出版年:IEEE Transactions on VLSI systems 13, 5 (2005).
第一著者: Thepayasuwan, N.
フォーマット: 論文
言語:英語
主題:
IP core placement.
IP core routing.
JPEG SoC.
Bus architecture synthesis.
Bus complexity.
Bus length.
Hardware/software codesign.
Hierarchical cluster growth algorithm.
Interconnect parasitic.
Latency optimization.
Layout conscious approach.
Network processor.
Select-eliminated method.
Special table structure.
Speed constraints.
Speed optimization.
System optimization.
Systems on chip optimization.
Task communication speed.