A novel FPGA architecture supporting wide, shallow memories.

A novel FPGA architecture supporting wide, shallow memories.

This paper investigates an architecture designed to implement wide, shallow memories on a field programmable gate array (FPGA). In the proposed architecture, existing configuration memory normally used to control the connectivity pattern of the FPGA is made user accessible. Typically, not all the sw...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 6 (2005).
Main Author: Oldridge, S.W
Format: Article
Language:English
Subjects:
FPGA architecture.
Benchmark circuit.
Configuration memory.
Embedded memory.
Field programmable gate array.
Switch blocks.
User accessible.
Wide/shallow memories.