Comparison of high-performance VLSI adders in the energy-delay space.

Comparison of high-performance VLSI adders in the energy-delay space.

In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, n...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Transactions on VLSI systems 13, 6 (2005).
Päätekijä: Oklobdzija, V.G
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
100 nm.
130 nm.
32 bit.
64 bit.
CMOS technology.
VLSI adders.
Design process.
Digital arithmetic.
Digital circuits.
Energy-delay characteristics.
Energy-delay optimization.
Estimation technique.