An efficient merging scheme for prescribed skew clock routing.

An efficient merging scheme for prescribed skew clock routing.

In ultra-deep submicron very large-scale integration (VLSI) designs, clock network layout plays an increasingly important role on determining circuit quality indicated by timing, power consumption, cost, power-supply noise, and tolerance to process variations. In this brief, a new merging scheme is...

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Bibliographic Details
Published in:IEEE Transactions on VLSI systems 13, 6 (2005).
Main Author: Chaturvedi, R.
Format: Article
Language:English
Subjects:
VLSI designs.
Benchmark circuits.
Buffered routing.
Clock cycle time.
Clock network layout.
Design automation.
Efficient merging scheme.
Nonzero skew routings.
Power consumption.
Power-supply noise.
Prescribed skew clock routing.
Process variation tolerance.
Timing performance.
Unbuffered routings.