A hardware-efficient technique to implement a trellis code modulation decoder.

This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algori...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 6 (2005).
第一著者:	Dinh, A.
フォーマット:	論文
言語:	English
主題:	0.18 micron. 1 Gbit/s. ASIC. CMOS. VLSI. Viterbi decoder. Decoding algorithm. Decoding throughput. Distance look-up table. Hardware complexity. Hardware-efficient technique. Trellis code modulation decoder. Trellis diagram.