A hardware-efficient technique to implement a trellis code modulation decoder.

This brief presents a new technique in implementing a very large-scale integration trellis code modulation (TCM) decoder. The technique aims to reduce hardware complexity and increase decoding throughput. The technique is introduced in the design of a Viterbi decoder. To simplify the decoding algori...

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Bibliographische Detailangaben

Veröffentlicht in:	IEEE Transactions on VLSI systems 13, 6 (2005).
1. Verfasser:	Dinh, A.
Format:	Artikel
Sprache:	English
Schlagworte:	0.18 micron. 1 Gbit/s. ASIC. CMOS. VLSI. Viterbi decoder. Decoding algorithm. Decoding throughput. Distance look-up table. Hardware complexity. Hardware-efficient technique. Trellis code modulation decoder. Trellis diagram.