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Wrapper design for multifrequency IP cores.

This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via t...

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Xehetasun bibliografikoak
Argitaratua izan da:IEEE Transactions on VLSI systems 13, 6 (2005).
Egile nagusia: Qiang Xu
Formatua: Artikulua
Hizkuntza:ingelesa
Gaiak:
Capture windows.
Core wrapper.
Embedded core.
Intellectual property cores.
Internal scan chains.
Internal shift frequency.
Multifrequency IP cores.
Multiple clock domains.
Power dissipation.
System-on-chip.
Test response capture.
Testability problems.
Tester bandwidth.
Tester channels.
Wrapper design.