Wrapper design for multifrequency IP cores.
This paper addresses the testability problems raised by intellectual property cores with multiple clock domains. The proposed solution is based on a novel core wrapper architecture and a new wrapper design algorithm. It is shown how multifrequency at-speed test response capture can be achieved via t...
| Publicado no: | IEEE Transactions on VLSI systems 13, 6 (2005). |
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| Autor principal: | |
| Formato: | Artigo |
| Idioma: | inglês |
| Assuntos: |