Design-for-testability for embedded delay-locked loops.

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that...

詳細記述

書誌詳細

出版年:	IEEE Transactions on VLSI systems 13, 8 (2005).
第一著者:	Egan, T.
フォーマット:	論文
言語:	English
主題:	DLL. SoC. TC. Application specific integrated circuit. Control voltage. Delay locked loops. Design for testability. Field-programmable gate array. Step response. System-on-chip. Test construct.