Design-for-testability for embedded delay-locked loops.

Design-for-testability for embedded delay-locked loops.

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that...

Szczegółowa specyfikacja

Opis bibliograficzny
Wydane w:IEEE Transactions on VLSI systems 13, 8 (2005).
1. autor: Egan, T.
Format: Artykuł
Język:English
Hasła przedmiotowe:
DLL.
SoC.
TC.
Application specific integrated circuit.
Control voltage.
Delay locked loops.
Design for testability.
Field-programmable gate array.
Step response.
System-on-chip.
Test construct.