Design-for-testability for embedded delay-locked loops.

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that...

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發表在:	IEEE Transactions on VLSI systems 13, 8 (2005).
主要作者:	Egan, T.
格式:	Article
語言:	English
主題:	DLL. SoC. TC. Application specific integrated circuit. Control voltage. Delay locked loops. Design for testability. Field-programmable gate array. Step response. System-on-chip. Test construct.