Cita APA (7th ed.)

Egan, T. Design-for-testability for embedded delay-locked loops. IEEE Transactions on VLSI systems.

Cita Chicago (17th ed.)

Egan, T. "Design-for-testability for Embedded Delay-locked Loops." IEEE Transactions on VLSI Systems .

Cita MLA (9th ed.)

Egan, T. "Design-for-testability for Embedded Delay-locked Loops." IEEE Transactions on VLSI Systems, .