Egan, T. Design-for-testability for embedded delay-locked loops. IEEE Transactions on VLSI systems.
Chicago Style (17th ed.) CitationEgan, T. "Design-for-testability for Embedded Delay-locked Loops." IEEE Transactions on VLSI Systems .
MLA (9th ed.) CitationEgan, T. "Design-for-testability for Embedded Delay-locked Loops." IEEE Transactions on VLSI Systems, .
Warning: These citations may not always be 100% accurate.