Exponentially tapered H-tree clock distribution networks.

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and...

Täydet tiedot

Bibliografiset tiedot

Julkaisussa:	IEEE Transactions on VLSI systems 13, 8 (2005).
Päätekijä:	El-Moursy, M.A
Aineistotyyppi:	Artikkeli
Kieli:	English
Aiheet:	H-tree clock network. Clock distribution network. Dynamic power dissipation. Inductive noise. Propagation delay. Signal transition time. Signal waveform. Tapered interconnect.